Introduction
This blog post is about the initial board bring up process of the Archer. Archer is the codename for our EPD laptop prototype at EI2030. This is not a comprehensive bringup guide, but rather document the issues I found and the corresponding solutions. The processor being used is the i.MX 7Dual.
DDR
DDR Stress Test
When there is no vaild boot devices, i.MX would enter mfgtools or USB recovery mode. In this mode the DDR stress test tool provided by NXP could be used to test the DDR read/ write leveling values. Though generally if the board is well designed, it should pass the stress test at room temperature without special calibration.
One thing to note is that, in Freescale SoCs, DDR3-800 is actually DDR3-792, and DDR3-1066 is actually DDR3-1056. Enter 396 MHz and 528 MHz respectively to test two modes.
DDR frequency
On i.MX7D, the DDR frequency could be set from anywhere up to 528MHz (DDR3-1056). By default, Boot ROM sets the DDR PLL to 1056MHz. Neither u-boot nor kernel would touch the DDR PLL settings. In kernel, the kernel would switch the DDR frequency between 24MHz, 99MHz, and 528MHz by choosing the clock source from CLKOSC, PFD396/4, and DDR PLL respectively. As an conclusion, to adjust the DDR clock frequency (for example, downclock from 1056 to 792), one could simply modify the DDR PLL settings in the DCD before u-boot starts.
Example:
/* Set DDR PLL to 792 MHz */ DATA 4 0x30360070 0x00113021 DATA 4 0x30360074 0x00113021 DATA 4 0x30360078 0x00113021 DATA 4 0x3036007C 0x00113021 DATA 4 0x30360070 0x00603021 DATA 4 0x30360074 0x00603021 DATA 4 0x30360078 0x00603021 DATA 4 0x3036007C 0x00603021 CHECK_BITS_SET 4 0x30360070 0x80000000 CHECK_BITS_SET 4 0x30360074 0x80000000 CHECK_BITS_SET 4 0x30360078 0x80000000 CHECK_BITS_SET 4 0x3036007C 0x80000000