Introduction & Overview

The following are the notes of getting U-Boot with SPL to boot from QSPI Flash on i.MX6ULL platform.

SPL is a stripped-down version of the full U-Boot, typically being loaded into on-chip SRAM. It is responsible for initializing the system (power, SDRAM, storage, etc.), loading the full U-Boot into SDRAM, and then jumping to the full U-Boot. (There is also a falcon mode, where SPL directly loads the kernel and jumps to the kernel.) Typically one doesn't need to use SPL on i.MX6 platform. The boot ROM is quite capable and extensible, to a point you may not even need the U-Boot at all.

In my case, I am using a board that requires the PMIC to be initialized before initializing DRAM. This could be implemented by using the plugin binary on the i.MX6 platform (essentially a small piece of code that would run before loading the full image), however in that case I would be completely on my own to figure out IO multiplexing, I2C controller programming, etc. An easier way is to use the SPL to set that up: it's designed to do that, after all. On top of that, I want the whole thing to run from SPI Flash.

Overall, I want the following features:

• U-Boot + SPL boots from QSPI Flash (W25Q32JV in my case)
• SPL should initialize the PMIC over I2C
• I start with a board that doesn't have anything:
  • eFUSE not programmed
  • Empty flash

I need the U-Boot + SPL to boot from the flash, but I also need to figure out how to set up the eFuse to let the processor try to boot from QSPI also write the U-Boot image into the empty flash. The plan would then be:

1. Load SPL into the processor's internal SRAM via USB and run the SPL to initialize the PMIC and DDR
2. Load the U-Boot into the DDR using SPL over USB and run the U-Boot
3. In the U-Boot, program the eFUSE
4. In the U-Boot, receive the U-Boot image over USB and write it into the flash.

The flash layout would look like this:

---- 0x00000 / Start ----
Empty (reserved for partition table)
---- 0x00400 / 1KB ----
QuadSPI Configuration Parameters Table, to be loaded by BROM
---- 0x01000 / 4KB ----
U-Boot SPL in imx image format, to be loaded by BROM
---- 0x12000 / 72KB ----
U-Boot in leagcy uImage format, to be loaded by SPL
---- 0xA0000 / 640KB ----
U-Boot environment variables
---- 0xA2000 / 648KB ----

Let's go over these steps.

Introduction

This blog post is about the initial board bring up process of the Archer. Archer is the codename for our EPD laptop prototype at EI2030. This is not a comprehensive bringup guide, but rather document the issues I found and the corresponding solutions. The processor being used is the i.MX 7Dual.

DDR

DDR Stress Test

When there is no vaild boot devices, i.MX would enter mfgtools or USB recovery mode. In this mode the DDR stress test tool provided by NXP could be used to test the DDR read/ write leveling values. Though generally if the board is well designed, it should pass the stress test at room temperature without special calibration.

One thing to note is that, in Freescale SoCs, DDR3-800 is actually DDR3-792, and DDR3-1066 is actually DDR3-1056. Enter 396 MHz and 528 MHz respectively to test two modes.

DDR frequency

On i.MX7D, the DDR frequency could be set from anywhere up to 528MHz (DDR3-1056). By default, Boot ROM sets the DDR PLL to 1056MHz. Neither u-boot nor kernel would touch the DDR PLL settings. In kernel, the kernel would switch the DDR frequency between 24MHz, 99MHz, and 528MHz by choosing the clock source from CLKOSC, PFD396/4, and DDR PLL respectively. As an conclusion, to adjust the DDR clock frequency (for example, downclock from 1056 to 792), one could simply modify the DDR PLL settings in the DCD before u-boot starts.

Example:

/* Set DDR PLL to 792 MHz */
DATA 4 0x30360070 0x00113021
DATA 4 0x30360074 0x00113021
DATA 4 0x30360078 0x00113021
DATA 4 0x3036007C 0x00113021

DATA 4 0x30360070 0x00603021
DATA 4 0x30360074 0x00603021
DATA 4 0x30360078 0x00603021
DATA 4 0x3036007C 0x00603021

CHECK_BITS_SET 4 0x30360070 0x80000000
CHECK_BITS_SET 4 0x30360074 0x80000000
CHECK_BITS_SET 4 0x30360078 0x80000000
CHECK_BITS_SET 4 0x3036007C 0x80000000

简介

以下介绍的裸机开发均基于i.MX6 Platform SDK完成，最后的版本于2013年发布，在使用gcc9编译时会遇到一些小问题，这里不做具体介绍。所有的开发均在Ubuntu 20.04上完成。目标平台为i.MX6D/Q，大部分也适用于i.MX6S/DL，但是对于i.MX6UL/ULL会需要较大改动。

编译与下载

PlatformSDK的Makefile中已经包含了产生目标镜像的代码，直接编译即可产生可以烧写进SD卡或者通过uuu载入的镜像，SPI Flash有待研究。（uuu是代替了MfgTools的跨平台i.MX USB烧录工具，可支持i.MX6\7\8）

可以直接使用如sudo uuu application.bin的命令下载程序至RAM运行。如果需要写成脚本，可以参考如下的写法：

uuu_version 1.2.135

SDP: boot -f path_to_the_application.bin
SDP: done

如果需要使用JTAG下载，则需要单独编写初始化DDR内存的初始化脚本，暂未进行测试。

串口

在EVK上默认调试串口为UART4，如果实际使用的板子并非使用UART4，则需要修改成板子上对应使用的串口。定义位于board/common/hardware_modules.c中。

内存配置

DDR控制器配置位于启动镜像的DCD区域中。如果使用的内存与EVK不同，则通常需要修改DCD配置。这部分数据位于board/mx6dq/board/dcd.c中。可以考虑使用官方的Programming Aid工具和DDR Stress Test工具来产生合适的DDR控制器配置。

不同板子拥有不同的内存容量。通常会区分出一部分不可cache内存用作DMA使用。主内存映射代码位于sdk/core/src/mmu.c中，具体的DMA内存设定定义在apps/common/platform_init.c中。以下为我在1GB RAM板子上使用的内存分割方案，仅供参考：

mmu_map_l1_range(0x10000000, 0x10000000, 0x20000000, kOuterInner_WB_WA, share_attr, kRWAccess); // First 512MB
mmu_map_l1_range(0x30000000, 0x30000000, 0x20000000, kNoncacheable, kShareable, kRWAccess); // Last 512MB

注：本文内容主要在LPC5528上测试，同样适用于55S2x和55S6x，不确定将来推出的其它系列是否也会同样适用。

高速USB

高速USB需要外部晶振才能使用，外部晶振频率可以在12\16\19.2\20\24\30\32MHz之间选择。由于官方开发板使用的是16MHz的晶振，所有例程和库也是使用16MHz的。如果使用了其它频率的晶振，可以通过设置PLL_SIC寄存器修改。官方库中设置的代码位于fsl_clock.c中：

USBPHY->PLL_SIC     = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06);

其中0x06即为PLL分频器设定值。以下为可选的值：

PLL_DIV_SEL	晶振频率
0x0	32 MHz
0x1	30 MHz
0x2	24 MHz
0x3	? MHz
0x4	20 MHz
0x5	19.2 MHz
0x6	16 MHz
0x7	12 MHz

```make ARCH=aarch32 CROSS_COMPILE=arm-linux-gnueabihf- PLAT=rk3288 AARCH32_SP=sp_min``` ```cp ~/arm-trusted-firmware/build/rk3288/release/bl32/bl32.elf ./bl31.elf``` ```pip3 install pyelftools``` ```tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin idbloader.img cat spl/u-boot-spl.bin >> idbloader.img``` ```make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- evb-rk3288-rk808_defconfig```