This time I am going to cover the memory access. Because a lot of DSP algorithms are quite heavy on memory access, so the handling of the memory access has a big impact on the performance. As a result, the memory access model on SHARC is not as simple as usually found on RISC processors. Note: modern RISC processors have much more sophisticated memory systems than SHARC+, but they are usually hidden away from the programmer.

Data Access

Basic Address Calculation

In SHARC, memory addresses are calculated by the DAG (Data Address Generator). When accessing memory, DAG uses 2 registers to calculate the address, one index (I) register, and one modify (M) register. The address is always index + modify. For example, if I want to access memory address 0xc0000000, I could load 0xc0000000 into the index register, then use constant 0 for the modify. The code would be as follows:

i4 = 0xc0000000;
m4 = 0;
r4 = dm(m4, i4);

DM refers to data memory, SHARC uses the syntax dm(modify reg, index reg) to access memory. To store into that address, just put dm on the LHS:

dm(m4, i4) = r4;

In SHARC, some modify registers always hold certain constant values: m5 is 0, m6 is 1, and m7 is -1. So the code could also be:

dm(m5, i4) = r4;

Immediate value as modify is also allowed. The width is limited to the different instruction encoding, which could be 6bit, 24bit, or 32bit. The index must come from a register.

dm(0, i4) = r4;

Say if I have two consecutive 32-bit values in the memory (for example, a complex number, or a 2D coordination) in the memory, pointed by i4, and now I want to load the first value (real part) into r4 and the second value (complex part) into r8, one way to achieve this is:

r4 = dm(m5, i4);
r8 = dm(m6, i4);

The first is modified by 0, and the second one is modified by 1. The modify value is counted in words, so 4 bytes by default.

I said one way, as there is another way. In the previous example, the modify is applied to the index then used for accessing the memory. This is called pre-index mode. There is also a post-index mode, where the index value is used for accessing the memory, then the modify is added to the index, and write back to the index register. In the pre-index mode, the indexing register is not updated, but in post-index mode, the indexing register is updated with the new address. So the previous code could be written as follows as well:

r4 = dm(i4, m6);
r8 = dm(i4, m6);

The pre-indexing mode is usually useful in accessing fields in a struct, while the post indexing mode is usually useful in accessing elements in an array within a loop.

Conditional Execution

This time we are going to take a look at how to implement the loop in SHARC+ assembly. We will be using the following simple code as an example:

// Calculate the Fibonacci number Fn, n need to be at least 2
int fibonacci(int n) {
    int a = 0, b = 1, f;
    for (int i = 1; i < n; i++) {
        f = a + b;
        a = b;
        b = f;
    }
    return f;
}

Normally, to implement it in assembly you would have code like this (RISC-V assembly for example):

    li t0, 0 # a
    li t1, 1 # b
    li t3, 1 # loop counter
loop_start:
    add t2, t0, t1
    mv t0, t1
    mv t1, t2
    addi t3, t3, 1
    blt t3, a0, loop_start

    mv a0, t2

A similar thing could be implemented in SHARC+ as well. Let's take a look at the code first (note the code is fairly inefficient, and we will improve that gradually):

    r2 = 1; // loop counter
    r8 = 0;
    r12 = 1;
loop_start:
    r0 = r8 + r12;
    r8 = r12;
    r12 = r0;
    r2 = r2 + 1;
    comp(r2, r4);
    if lt jump loop_start;

Aside from the syntax difference, one major difference is that SHARC+ uses flags to do the conditional jump, so a comparison instruction might be necessary before the condition. In this example, the loop counter is compared against the end condition. If the loop counter is less than (lt) the end condition, it jumps back to the beginning of the loop. If it is counting down, then we could use flags that directly compare the last result with zero. There are other conditional codes (and there complementary) available:

Prologue

During the past year, I found myself writing a lot of SHARC+ assembly code. For me, the SHARC is quite an interesting ISA. It's in some way very different from other general-purpose RISC processors. From a quick search, there is no SHARC+ assembly programming tutorial I can find online. As a result, I am writing one myself. This is more or less a quick guide instead of a complete document. For the latter, please read the official SHARC+ PRM (programming reference manual).

This guide assumes knowledge of the C programming language and common computer architecture. Familiarity with at least one kind of assembly language (x86, arm, MIPS, z80, etc.) would help a lot.

If you are intending to learn to program the SHARC+ DSP, hope this tutorial will help you. If you are just a computer architecture enthusiast like me, just wanting to learn about this architecture, hope you would find this tutorial interesting.

(Figure: SHARC+ core diagram, source: SHARC+ PRM)

Introduction

SHARC, which stands for Super Harvard Architecture Single-Chip Computer, is a series of DSPs designed and sold by Analog Devices Inc since 1991. By the time of writing (2021), there are 3 variants of the ISA:

• SHARC (correspond to SHARC-V core)
• TigerSHARC
• SHARC+ (correspond to SHARC-XI core)

This series of tutorials only apply to SHARC and SHARC+. All the processors in the 215xx series use the SHARC+ core. About the core name, SHARC-V simply means it has a 5-stage pipeline, and SHARC-XI simply means it has an 11-stage pipeline. SHARC+ is backward compatible with SHARC.

本期，我们将继续讲解之前没有讲完的Verilog代码。上一期的教程已经介绍了Verilog最核心的一些操作，本期则将介绍一些有用的其它操作，他们最终也可以用核心的操作代码表示出来，但是通常而言编写起来更为简便。本期同样会介绍仿真工具的使用，在开发过程中非常有用。不过在开始新的内容之前，先来讲讲上一次留的作业。

上期练习

上期留了一个作业，就是实现第五期里面讲过的状态机。这里首先复述一下第五期的状态机：假设一个贩卖机，只卖矿泉水，价格定为2元，只接受1元硬币或者5角硬币，多不找零，设计一个状态机来描述它的行为。这个机器的话，它有两个输入，投入5角或者投入1元；以及一个输出，是否已经付了足够多的钱。

如同之前一样，假设表示投入5角硬币的信号叫a，表示投入1元硬币的信号叫b，输出是否已经付够钱的信号叫c。同时定义这个系统有S0-S4一共5个状态，分别表示当时已经投入了0、0.5、1、1.5和2元。

要用Verilog来实现这个状态，第一步肯定是先写一个整体的模块框架，再往里面加入东西。于是参考上期的声明module的方法，先写下如下的代码：

module vending(
    input clk,
    input rst,
    input a,
    input b,
    output c);

endmodule

上面的代码定义了一个叫vending的模块，有四个输入，clk、rst、a和b，一个输出c，主体没有内容。clk提供时钟，rst提供复位。首先来考虑输出吧。状态机的输出是由当前状态决定的，所以需要有一个变量（触发器）来保存当前的状态，比如叫做state：

reg [2:0] state;

有了state之后就可以描述输出的逻辑了。一种方法是直接用第五期的逻辑表达式：

assign c = state[2] && !state[1] && !state[0];

首先，恭喜大家，一直跟到了这个教程的第五期。如之前所说，从本期开始，我们将正式开始使用Verilog给FPGA写代码。而要写的东西，这是第2-4期里面介绍过的组合逻辑，时序逻辑和状态机。而Verilog也将会是在这之后用于描述各种硬件的语言。

其实读Verilog代码本身并不复杂，有软件编程经验的人就不难理解代码的含义，毕竟其语法和C语言很接近；但是写Verilog代码，就是另外一回事了。Verilog里面有很多和C接近的概念和语句，比如赋值，比如if-else，比如for循环，等等。但是Verilog的目标结果，逻辑门，却又和C的目标结果，程序，太不一样了。他们确实某种程度上是接近的语言，但是语言里有接近的东西并不表示他们就能实现接近的功能。或者反过来，想要实现同样的功能，未必会使用接近的方法。所以说，学习Verilog最好的捷径就是不要走捷径，从数字电路开始学习，而并非一开始就学习代码，以至于被代码所迷惑。

Verilog程序模块

Verilog程序如同其它的编程语言程序一样，有它特定的源文件格式。Verilog的源代码后缀名为.v，每一个Verilog文件都是一个Verilog模块，各位可以类比为编程语言中的函数。基本格式如下：

module 模块名(模块输入输出信号);
    模块内容
endmodule

其中这个模块名通常需要和对应的文件名相同，同一个文件只定义一个模块，比如adder.v里就应该只定义一个叫adder的模块。这个要求和Java对类的要求很相似。

输入输出信号则是接近一个函数的返回值和参数，只不过在Verilog里并不把参数和返回值放到不同的地方定义，而是都写在一起。所有的参数或者返回值，最终都只是导线而已。而导线根据驱动信号的方向，可以有输入和输出区别。至于需要多少个输入多少个输出，那就取决于具体的程序了。

模块内容则是模块内部的逻辑，也许有代码块（always），也许只是一些简单的接线（assign）。不过别忘了，一切最后都会回归到硬件。

最后说说模块的实例化，或者说调用。如前面所说，模块类似于软件编程语言里面的函数，它也确实有对应的函数名，参数，返回值等等类似的概念。那么要使用这个“函数”，自然也就需要一种调用的方法。只不过，Verilog里的调用，并不是像编程语言一样在特定位置执行特定代码（毕竟本身就没有“执行代码”这种操作），而是新复制一份这个模块所表示的硬件，然后连接对应的导线。这一点在参数的定义时其实也就有所体现，定义的输入输出并非是变量，而是导线， 也就是说，传递的内容并不是数值，而是连接。一旦连接被确定，传输就是时时进行的（因为线被连接上了）。这个和编程语言里的调用非常不一样，所以务必进行区分。具体的例子我们之后就会提到。