module ZephRay;

今朝有鱼今朝摸

Category

  • 摄影
  • 玩机
  • 硬件坑
  • 翻译
  • 软件坑
  • 随记

Tags

  • LCD
  • 点屏
  • 单片机
  • 计算器
  • 事
  • FPGA
  • STM32
  • 摄影
  • 古董
  • Verilog
  • 测评
  • 笔记本
  • 改造
  • Linux
  • 移植
  • ARM
  • 树莓派
  • 小动物
  • nspire
  • 教程
  • 景
  • 项目
  • LED
  • GameBoy
  • EPD
  • 3DS
  • 晒机
  • IBM
  • HP
  • SDL
  • ThinkPad
  • Kindle
  • 82ES
  • Minecraft
  • 花
  • Chiptune
  • 仙剑奇侠传
  • Assembly
  • 手办
  • 贴图
  • 演讲
  • NDSL
  • Nikon

Recent replies

  • 城市猎人 发表于「IBM ThinkPad 560E (Type 2640) 简单展示」
  • Khiemmy 发表于「On the way to overclock the TI nspire CX II calculator」
  • critor 发表于「On the way to overclock the TI nspire CX II calculator」
  • ZephRay 发表于「On the way to overclock the TI nspire CX II calculator」
  • critor 发表于「On the way to overclock the TI nspire CX II calculator」
  • imbushuo 发表于「About Me」
  • 070 发表于「古董电脑选型」
  • Thermit 发表于「About Me」
  • 盛崖鱼 发表于「About Me」
  • Wenting Zhang 发表于「About Me」

My

RSS (中文优先)
RSS (English preferred)

坑 / Projects
关于我 / About
简历 / CV
破烂采购计划 / Craplist
古董电脑选型
SM83(GB CPU)指令编码
Linux PI 1M位跑分
Coremark跑分
音质参考

淘宝杂货铺
Bilibili空间
GitHub

Links

cnVintage古董电子论坛
cnCalc计算器论坛

Keshuai Xu
家骅的锦绣谷
>Lithia's Core
ntzyz's space
丘丘塔台
tonoko.moe
kasora's blog
447f.Misaka
paizhang.info
spinmry实验室
Hikari Calyx Tech.
春上冰月的博客
初音没有来
FindHao
Test2g
Shell Bin
LEAFER x LAB
标签:古董

Dramite Design Note (1)

2021 年 1 月 19 日分类:硬件坑#FPGA#古董

Introduction

Dramite aims to build a small PC-compatible SBC based on an Intel 80386DX processor and an FPGA to emulate a custom chipset. There are several reasons why I am building a 386 PC in 2021:

  1. To learn Chisel
  2. I happen to have lots of 386DX chips lying around
  3. Just because

I expect this to be a long term project, and this is the first project log. I am trying not to explain too many details in these notes. This should not be a tutorial, but just some facts.

Overall Architecture

An FPGA is used as the bridge. It would handle everything from memory controller, floating point co-processor, to legacy IO bus, USB keyboard and mouse IO port emulation.

On a high level, the design would be simply connect the 386DX to the FPGA, done. However, it is still unclear how to approach everything in the FPGA. We could try to replicate things that exists on real 386 motherboards, such as direct connect between 386 and 387, SRAM caches, ISA buses, multiple devices attached to the ISA buses, etc. But this might not be the optimal solution, and sometimes may not even apply. For example, we would not have FPM/EDO RAMs on our board. Instead I would like to start from a performance perspective, looking at what we have, and see what would be the optimal architecture design.

Local Bus

The processor is the 386DX, I obviously couldn't modify the internals of the processor to enhance the performance. But I want to ensure I get the most out of it. The best I can do is to allow the bus access to finish as quick as possible (0 wait state).

The 386 also allows the bus to be pipelined, so it would sends the address one cycle eariler, to give the memory more time to access. Unfortunately this function also comes with a cost:

Table comes from Intel 80386DX Microprocessor Hardware Reference Manual. As you may see, by enabling the pipelining, we lose 9% of performance. This is still better than 1 wait state, which we loose 19% of performance. We shall see how these means in terms of the time for the FPGA to respond.

In the non-pipelined case, looking at CYCLE 1, the 386DX outputs the valid address and control signals on the falling edge of CLK in T1. Means the FPGA could latch the data in on the rising edge of CLK in T1. The 386DX expects the data to be ready on the falling edge of CLK in T2, means the FPGA should put out the data on the rising edge of CLK in T2. The FPGA has exactly one cycle time in CLK to prepare the data. CLK runs at 33MHz, translates to a cycle time of 30ns. The whole bus cycle lasts for 60ns, and FPGA has 30ns to prepare the data.

If one wait state is added, such as in CYCLE 3, the whole cycle is now 90ns. And the FPGA has 60ns to prepare the data in this case.

What about pipelined?

The bus cycle time is still 60ns, but the FPGA now gets 60ns to prepare the data. Remember this is with 9% of performance penalty.

In conclusion, to achieve the absolutely best performance, we use non-pipelined mode and supply the data in single cycle. It is currently unknown if it would provide any performance improvement if I mix both modes.

Cache

Obviously, some form of cache is needed to provide the data in 30ns. But what kind of?

The on-chip memory of FPGA would certainly be fast enough to provide data in 30ns.

Off-chip high speed SRAMs would also be able to provide data in 30ns. We could use the normal SRAM chips to build the cache if we want, at the cost of layout complexity and IO pin usage.

FPGA on-chip memory size, just for reference.

DRAM

How slow is the DRAM?

Using the DDR3 MIG on Aritx-7, with AXI interface, we could see the typical read latency:

The time difference is 63799.5ns - 63607.5ns = 192ns.

But if we think the DRAM controller is probably not very optimized, what's is the time it takes the DDR3 memory itself to read the data?

Much faster. 63746ns - 63714ns = 32ns, just a little above the cycle time that 386 would take.

But the cache is still needed. It is just the cache miss penalty wouldn't be too bad.

Hardware IO Planning

  • 80386DX: 79 5V IOs (with address pipeline mode disabled, 32 bit only, no bus take-over)
  • RGMII: 16 1.5V/1.8V/2.5V/3.3V IOs
  • Audio: 3 1.8V/3.3V IOs
  • USB: 11 1.8V/3.3V IOs + 1 RESET (could be open-drain)
  • SDIO: 6 3.3V IOs
  • HDMI: 4 TMDS pairs (GTP + voltage translator, or 1.8V IO)
  • DDR3 SODIMM: 118 1.5V IOs

The 80386DX needs voltage translator, and best 3.3V-5V for minimal propagation delay. Plus 1 direction control pin for databus, so that's 80 3.3V IOs. Basically means 2 of the IO banks needs to be 3.3V.

The DDR3 uses 3 IO banks, so 3 of the IO banks needs to be 1.5V.

And some common I2C control channels for audio, SPD, HDMI, etc. Count as 4, any voltage.

XC7A35T has 6 available IO banks:

  • IO Bank 14: 50 IOs, 1.5V
  • IO Bank 15: 50 IOs, 1.5V
  • IO Bank 16: 50 IOs, 1.5V
  • IO Bank 34: 50 IOs, 3.3V
  • IO Bank 35: 50 IOs, 3.3V
  • IO Bank 216: 4 TX pairs and 4 RX pairs

In total it has 150 1.5V IOs, 100 3.3V IOs, 4 TX pairs, and 4 RX pairs.

In total 134+5 1.5 IOs, 100 3.3 IOs, 4 TX pairs needed. It still has 11 1.5V IOs and 4 RX pairs left.

IBM Personal System/2 Model 33 "E" 简单展示

2018 年 4 月 1 日分类:玩机#测评#古董#IBM

不同的人对电脑的外形有着不同的喜好,为此也催生了许许多多不同的外形设计。大的,小的;朴素的,花哨的;棱角分明的,圆润流畅的,等等。我个人呢,就是比较喜欢小机箱的电脑,觉得通常而言会显得比较精致一些。虽然现在小机箱系统有不少,组装机有各种小容量的机箱选择,品牌机也通常提供USFF和SFF的选项,但是在上世纪,486、586那个年代,小体积的电脑并不多。而今天要展示的,就是那些为数不多的小机箱古董机中之一——IBM Personal System/2 Model 33 "E"(简称PS/2 E)。

基本参数

  • CPU: IBM 486SLC2-50
  • RAM: 4 MB
  • 显卡: IBM XGA-2
  • 声卡: Aztech Sound Galaxy Pro16
  • 总线: ISA (AT)
MORE

AlphaSmart Pro 便携式字处理器

2018 年 2 月 19 日分类:玩机#古董

字处理器,这种品类的产品放在今天,如果要说还有什么意义的话,可能只能说是“纯粹 专注 激情不已”。然而正是这个听着很空泛的玄学意义,让电子字处理器类的产品在传统打字机淘汰后一直存活至今(如Freewrite)。而今天要展示的,是其中一款不起眼但却在教育领域广为使用的产品:AlphaSmart Pro。

这款产品发布于1995年,是两年前初代AlphaSmart的升级版本,主要升级是加入了PC连接功能(前代产品只能通过ADB连接Mac。)整体的外观设计就很有Mac味,这种Mac味在后续的产品上也有体现,如后代产品模仿了iBook G3贝壳机的造型设计。实际上,该公司的创始人就是苹果的员工,他们要制造字处理器的想法在被苹果否认后才自立门户开始生产,初期主要客户是中小学的老师,他们想要为学生提供一款专注于书写的工具。

MORE

IBM ThinkPad 750C & 755C (Type 9545) 展示

2018 年 1 月 16 日分类:玩机#笔记本#古董#ThinkPad#测评

有段时间没有写过测评了,这次为大家带来的是第一款登上太空的电脑——ThinkPad 750C以及其小改款755C的简单展示。

基本信息

  • 产品名称:ThinkPad 750C / 755C
  • 厂商:IBM
  • 类别:Laptop
  • 发布年份:1993 / 1994年
  • CPU:Intel 80486SL-33 / 80486DX2-50
  • 硬盘:170MB / 340MB HDD
  • 软驱:1.44MB / 2.88MB
  • RAM:板载4MB-8MB 外扩16MB
  • 屏幕类型:TFT液晶显示器,TN Normal-White,256色
  • 屏幕规格:640x480 10.4"
  • 音源:CS4248 WSS
  • 接口:2xPCMCIA + MIC + 耳机 + 端口扩展器接口
  • 供电:AC + Li-Ion电池
  • 质量:2.8 kg (含电池)
  • 操作系统:DOS / Windows 3.x

展示

这个机子本身设计没有太多的亮点,所以就稍微放几张图看看好了。

MORE

SONY PCG-SR5K 笔记本展示

2017 年 11 月 9 日分类:玩机#古董#笔记本

大家好。这次展示的机子大概没有什么太多的特殊点,也没有什么历史背景,就是一台普通的笔记本罢了。个人还是比较喜欢这个机子的,所以今天简单展示一下吧。

基本参数

  • CPU: Intel Mobile Pentium III 500MHz
  • RAM: 标准128MB 最大256MB
  • 硬盘: IBM TravelStar 9GB
  • 屏幕: 10.4” p-Si TFT LCD 800x600
  • 音源: Yamaha DS-XG
  • 质量: 1.4kg

外观

这台机器的外观个人认为设计上还是比较现代的。相比年代接近的R505和Z505系列,我还是更加喜欢这款笔记本的造型。

image dsc-0004jpg.jpeg

A面是那个时候索尼的典型设计,也就是喷漆。这些机器到了今天的话,多多少少都会有一些掉漆的问题。

MORE
  • «
  • 1
  • 2
  • 3
  • »
Copyright © 2009-2019 Wenting Zhang. All rights reserved.
Unless otherwise noted, content on this blog is licensed under CC BY-SA 4.0.